1. Field
The embodiments discussed herein relate to a multiphase clock generation circuit.
2. Description of Related Art
The multiphase clock generation circuit generates a multiphase clock from a reference clock. For example, the multiphase clock generation circuit may be embedded in the wireless communication device.
Related art is disclosed in Japanese Unexamined Patent Application Publication No. 2002-176354, Japanese Unexamined Patent Application Publication No. 2008-124966, a nonpatent literature ISSCC 2001: 10.4 “A 1.75 GHz Highly-Integrated Narrow-Band CMOS Transmitter with Harmonic-Rejection Mixers”, a non-patent literature ISSCC 2006: 26.6 “An 800 MHz to 5 GHz Software-Defined Radio Receiver in 90 nm CMOS”, and the like.